1. Field of the Invention
The present invention relates to a liquid crystal display apparatus and its driving method as well as a liquid crystal display system, particularly to an active matrix type liquid crystal display apparatus of a dot successive driving system for successively driving respective pixels arranged in a matrix shape for respective line (row) in units of pixels and its driving method as well as a liquid crystal display system using the liquid crystal display apparatus.
2. Description of the Related Art
An explanation will firstly be given of a first problem which the present invention intends to resolve. According to an active matrix type liquid crystal display apparatus, normally, as switching elements of respective pixels, thin film transistors (TFT) are used. FIG. 7 shows an example of a constitution of such an active matrix type TFT liquid crystal display apparatus. In this case, for simplicity, there is shown, for example, a case of an arrangement of four rows and four columns of pixels.
Pixels 101 are arranged in a matrix shape at intersecting portions of respectives of gate lines Vg1 through Vg4 and respectives of signal lines sig1 through sig4 in FIG. 7. The pixels 101 are constructed by a constitution having thin film transistors TFTs gate electrodes of which are connected to the gate lines Vg1 through Vg4 and source electrodes (or drain electrodes) of which are connected to the signal lines sig1 through sig4 and hold capacitors Cs one electrode of each of which is connected to the drain electrode (or source electrode) of the thin film transistor TFT. Further, in this case, for simplifying the drawing, a liquid crystal cell LC is omitted. A pixel electrode of the liquid crystal cell LC is connected to the drain electrode of the thin film. transistor TFT.
According to the pixel structure, opposed electrodes of the liquid crystal cells LC, not illustrated, and other electrodes of the hold capacitors Cs are connected to a Cs line 102 commonly among the respective pixels. Further, direct current voltage is applied on the opposed electrodes of the liquid crystal cells LC, not illustrated, and the other electrodes of the hold capacitors Cs as common voltage Vcom via the Cs line 102.
A scanning driver 103 carries out a processing of selecting the pixels 101 in units of rows by successively scanning the gate lines Vg1 through Vg4 at every vertical period (1 field period). In the meantime, a source driver 104 carries out a processing of successively sampling, for example, image signals video1 and video2 inputted by two routes at every horizontal period (1H) and writing sampled image signals to the pixels 101 of a row selected by the scanning driver 103.
According to the source driver 104, specifically, sampling switches sw1 through sw4 are alternately connected between the respective signal lines sig1 through sig4 of the pixel unit and respective input signal lines 105-2 and 105-1 of the image signals video2 and video1 and the sampling switches sw1 through sw4 in pairs of twos are successively made ON in response to sampling pulses Vh1 and Vh2 successively outputted from respective transmitting stages 106-1 and 106-2 of shift registers.
In the case of the active matrix type TFT liquid crystal display apparatus having the above-described constitution, as a system of driving thereof, there is known a dot successive driving system for successively driving the respective pixels at every line (every row) in units of pixels. In carrying out the dot successive driving, in the case of a 1H inversion driving system, in one horizontal line, the sampling switches sw1 through sw4 are made ON in a dot successive manner by the sampling pulses Vh1 and Vh2 and as shown by FIG. 8, image signals in the same polarity (video1 and video2 are in the same polarity) are-written to the respective pixels 101 via the respective signal lines sig1 through sig4. As a result, as shown by FIG. 9, the image signals in the same polarity (+/−) are written to contiguous left and right ones of the pixels.
In the meantime, resistor components RCs are present between the contiguous left and right ones of the respective pixels in the Cs line 102, further, parasitic capacitances c1 are present between the Cs line 102 and the signal lines sig1 through sig4 and accordingly, a differentiating circuit is formed by the resistor component RCs, the hold capacitor Cs and the parasitic capacitance c1 and accordingly, in writing the image signals video1 and video2, the image signals video1 and video2 are inputted to the Cs lines 102 and the gate lines Vg1 through Vg4 via the hold capacitors Cs and the parasitic capacitances c1.
Thereby, as shown by FIG. 8, potential VCs of the Cs line 102 is deviated in a direction of the same polarity of the image signals video1 and video2 (ΔVCs) and accordingly, cross talk in the horizontal direction (hereinafter, abbreviated as horizontal cross talk) shown by FIG. 10 becomes significant, a failure in shading is caused and image quality is considerably deteriorated. In FIG. 10, a portion indicated by a black region designates an actual image 111 which is actually displayed, a false image (a portion indicated by a dotted region) 112 is produced on a side of the actual image 111 in the horizontal direction.
Further, during a time period in which the pixel 101 holds pixel information in one field period, potential Vsig of the signal lines sig1 through sig4 is deviated at every “H” (ΔVsig). Here, in the case of the 1H inversion driving system, the polarity of the image signals written to the contiguous left and right ones of the pixels stays the same and accordingly, the deviation ΔVsig of the potential of the signal lines sig1 through sig4 is increased.
Further, in respectives of the pixels 101, parasitic capacitances are present also between the source/drain electrodes of the thin film transistors TFT and the respectives of the signal lines sig1 through sig4 and accordingly, the deviation ΔVsig of the potential of the signal lines sig1 through sig4 is inputted to the pixels by source/drain couplings of the thin film transistors and accordingly, cross talk in the vertical direction (hereinafter, abbreviated as vertical cross talk) becomes significant to thereby constitute a factor of a failure in image quality similar to the horizontal cross talk.
There is provided the dot inversion driving system as a driving method of preventing a deviation ΔVcs of the potential of the Cs line 102 and the deviation ΔVsig of the potential of the signal lines sig1 through sig4 from causing. In the case of the dot inversion driving system, the two image signals video1 and video2 are inputted in inverse polarities (however, similar to the case of the 1H inversion driving system, respective polarities of the image signals video1 and video2 in the inverse polarities are inverted at every “H”). Thereby, when the switches sw1 and sw2 are made ON in response to the sampling pulse Vh1, as shown by FIG. 11, the image signal video1 and the image signal video2 are simultaneously written in the inverse polarities and accordingly, the deviations ΔVcs and ΔVsig of the potential are canceled between the contiguous ones of the pixels and accordingly, there poses no problem of the failure in image quality as in the case of the 1H inversion driving system.
However, in the case of the above-described dot inversion driving system, as is apparent from FIG. 12, the polarities of the image signals video1 and video2 written to the contiguous left and right ones of the pixels differ from each other and accordingly, influence of an electric field of a contiguous one of the pixel is effected. Then, a domain (light deficient domain) 122 is produced at corners of an opening portion 121, the portion cannot be used as the opening portion 121 and accordingly, a light shielding portion 123 is obliged to constitute as shown by FIG. 13. Therefore, an aperture ratio of the pixel is lowered, the transmittivity is reduced and accordingly, the contrast is lowered and a failure in image quality is resulted.
Next, a description will be given of a second problem which the present invention intends to resolve. According to the active matrix type liquid crystal display apparatus, normally, the thin film transistor (TFT) is used as the switching element of the respective pixel. In the case of the active matrix type TFT liquid crystal display apparatus, in carrying out the dot successive driving, according to the 1H inversion driving system of inverting the polarity of an image signal inputted to the respective pixels is inverted at every “H” (notation H designates a horizontal period), when charge/discharge current caused by writing the image signal to the signal line wired at respective column of the pixel unit is large, a vertical streak appears on a display screen.
There is known a precharge system for previously writing a precharge signal level prior to writing the image signal in order to restrain the charge/discharge current caused by writing the image signal as less as possible. FIG. 18 shows an example of a constitution of such an active matrix type TFT liquid crystal display apparatus of the dot successive precharge system. In this case, for simplicity, there is shown a case of an arrangement of four rows and four columns of pixels as an example.
In FIG. 18, pixels 101A are arranged in a matrix shape at intersecting portions of respectives of gate lines Vg1A through Vg4A and respectives of signal lines sig1A through sig4A. The pixels 101A are constructed by a constitution having thin film transistors TFT gate electrodes of which are connected to the gate lines Vg1A through Vg4A and source electrodes (or drain electrodes) of which are connected to the signal lines sig1A through sig4A, respectively, and the hold capacitors Cs the one electrode of each of which is connected to a drain electrode (or source electrode) of the thin film transistor TFT. Further, in this case, for simplifying the drawing, the liquid crystal cell LC is omitted. The pixel electrode of the liquid crystal cell LC is connected to the drain electrode of the thin film transistor TFT.
According to the pixel structure, the opposed electrode of the liquid crystal cell LC, not illustrated, and the other electrode of the hold capacitor Cs are connected to a Cs line 102A commonly among the respective pixels. Further, predetermined direct current voltage is applied on the opposed electrode of the liquid crystal cell LC, not illustrated, and the other electrode of the hold capacitor Cs as the common voltage Vcom via the Cs line 102A.
A scanning driver 103A is arranged, for example, on the left side of the pixel unit. The scanning driver 103A carries out a processing of selecting the pixels 101A in units of rows by successively scanning the gate lines Vg1A through Vg4A at every vertical period (every field period). Further, a source driver 104A is arranged, for example, on an upper side of the pixel unit and a precharge driver 105A is arranged, for example, on a lower side, respectively.
The source driver 104A successively samples an image signal video which is inputted via an image signal line 106A and polarities of which are inverted at every “H” and writing the sampled image signal to the pixels 101A of a row selected by the scanning driving 103A. That is, sampling-switches hsw1A through hsw4A connected between the respective signal lines sig1A through sig4A of the pixel unit and the image signal line 106A, are successively made ON in response to sampling pulses Vh1 through Vh4 successively outputted from respective transmitting stages 107-1A through 107-4A of shift registers.
The precharge driver 105A carries out a processing of successively sampling a precharge signal level Psig inputted in a polarity the same as a polarity of the image signal video via a precharge signal line 108A and writing the sampled precharge signal to the pixels 101A of a row selected by the scanning driver 103A prior to the image signal video. That is, sampling switches psw1A through psw4A connected between the respective signal lines sig1A through sig4A of the pixel unit and the precharge signal line 108A, are successively made ON in response to sampling pulses Vp1 through Vp4 successively outputted from respective transmitting stages 109-1A through 109-4A of shift registers.
Next, an explanation will be given of operation of the active matrix type TFT liquid crystal display apparatus of the dot successive precharge system having the above-described constitution in reference to timing charts of FIG. 19.
First, the sampling pulses Vp1 through Vp4 are successively outputted in synchronism with a horizontal clock CK in response to a precharge start pulse Pst from the respective transmitting stages 109-1A through 109-4A of the shift registers in the precharge driver 105A. In the meantime, the sampling pulses Vh1 through Vh4 are successively outputted in synchronism with the horizontal clock CK while being retarded by a half clock of the horizontal clock CK relative to the sampling pulses Vp1 through Vp4 in response to a horizontal start pulse Hst from the respective transmitting stages 107-1A through 107-4A of the shift registers in the source driver 104A.
Thereby, at the respective rows successively selected by the scanning driver 103A, firstly, the precharge signal levet Psig is written to the signal line sig1A by making ON the sampling switch psw1A in response to the sampling pulse Vp1A, successively, the image signal level video is written to the signal in sig1A by making ON the sampling switch hsw1A in response to the sampling pulse Vh1. Thereafter, the precharge signal level Psig and the image signal level video are written to the signal line sig1A in the dot successive manner by the sampling pulses Vp2 through Vp4 and the sampling pulses Vh2 through Vh4.
In this way, according to the active matrix type TFT liquid crystal display apparatus, prior to writing the image signal video to the signal lines sig1A through sig4A, by previously writing the precharge signal level Psig in the dot successive manner, a signal level in writing the image signal video can be reduced and the charge/discharge current in writing the image signal video can be restrained and accordingly, production of the vertical streak can be prevented.
In the meantime, the precharge signal level Psig must be set to a gray level which is easiest to see the vertical streak. However, when the precharge signal level Psig is set to the gray level, in displaying a window pattern or the like, there is produced cross talk in the vertical direction (hereinafter, abbreviated as vertical cross talk) owing to a difference of a light leakage amount between the source and the drain of the pixel transistor (thin film transistor) depending on locations of image and therefore, the image quality is deteriorated.
In order to prevent the vertical cross talk from being produced, the precharge signal level Psig may be set to a black level whereby leakage current between the source and the drain of the pixel transistor can be made uniform over an entire screen. However, when the precharge signal level Psig is set to the black level, the above-described vertical streak is produced. That is, the vertical cross talk and the vertical streak are in a relationship of tradeoff.
Hence, the inventors have proposed an active matrix type TFT liquid crystal display apparatus of a so-to-speak two step integral precharge system in which the black level and the gray level are precharged integrally in two steps. FIG. 20 shows an example of a constitution of such an active matrix type TFT liquid crystal display apparatus of the two step integral precharge system. Further, this constitution differs from the active matrix type TFT liquid crystal display apparatus of the dot successive precharge system only in the constitution of the precharge driver.
That is, according to a precharge driver 105′A, whereas a precharge signal level Pstg of two steps having the black level and the gray level is inputted through the precharge signal line 108A, the sampling switches psw1A through psw4A connected between the respective signal lines sig1A through sig4A and the precharge signal line 108A, are applied commonly with a precharge control pulse Pcg via a control line 110A.
FIG. 21 shows a timing relationship in the case of the two step integral precharge system. As is apparent from timing charts thereof, the precharge control pulse Pcg is produced in a horizontal blanking period. Thereby, in the horizontal blanking period, firstly, the black level and successively the gray level of the two step precharge signal Pstg are integrally written to the signal lines sig1A through sig4A, thereafter, the image signal video is written to the signal line sig1A through sig4A in the dot successive manner.
In this way, by inputting the precharge signal Pstg of the two steps in the horizontal blanking period and carrying out the integral precharging to the signal lines sig1A through sig4A, firstly, the black level is written to thereby eliminate the vertical cross talk produced owing to the leakage current between the source and the drain of the pixel transistor and thereafter, the gray level is written thereto to thereby eliminate the vertical streak produced owing to the charge/discharge current in writing the image signal video.
However, according to the two step integral precharge system, although there is achieved an excellent effect of capable of improving failures in image quality by eliminating both of the vertical cross talk and the vertical streak, there poses a problem in which the system is not applicable to an image format having a short horizontal blanking period since the precharging operation needs to carry out in the two steps of the black level and the gray level in the horizontal blanking period.
In recent years, there is a tendency of increasing a number of pixels in accordance with high resolution formation, when the number of pixels increases, the horizontal blanking period of the image format is shortened and according to display standards of high vision (HD) and UXGA (ultra extended graphics array), the horizontal blanking period is much shortened. Taking an example of the UXGA display standard, the pixel unit is constituted by horizontal 1600 pixels×vertical 1400 pixels, the horizontal blanking period is, for example, 2.4 μsec and accordingly, the precharge time period cannot be secured by a delay in a scanning pulse applied to the gate of the respective pixel transistor via the gate lines Vg1A through Vg4A. Accordingly, the two step integral precharge system is not applicable.